Configurable bus

ABSTRACT

A device includes an analog block array, a first analog bus segment coupled to the analog block array, a second analog bus segment coupled to the analog block array, and a third analog bus segment coupled to the analog block array. The device also includes a first I/O pin selectively couplable to the first analog bus segment, a second I/O pin selectively couplable to the second analog bus segment, and a third I/O pin selectively couplable to the third analog bus segment. A first switch is configured to selectively propagate a first analog signal on the first analog bus segment to the second analog bus segment, and a second switch is configured to selectively propagate a second analog signal on the first analog bus segment to the third analog bus segment. In a first mode of operation, the first and second switches are open. In a second mode of operation, the first switch is closed. In a third mode of operation, the second switch is closed.

CROSS-REFERENCE TO RELATED APPLICATION

The present application is a continuation application of U.S. Non-Provisional application Ser. No. 14/818,080, filed Aug. 4, 2015, which claims priority to U.S. Non-Provisional Application Ser. No. 11/698,660, filed Jan. 25, 2007, now U.S. Pat. No. 9,098,641, issued on Aug. 4, 2015, which claims priority to U.S. Provisional Application No. 60/763,509, filed Jan. 30, 2006, all of which are incorporated by reference herein in their entirety.

TECHNICAL FIELD

This disclosure relates generally to electronic buses, and in particular but not exclusively, relates to configurable electronic buses.

BACKGROUND INFORMATION

Conventional multiplexers are typically limited to an N to 1 configuration. That is, each input to the multiplexer is a point-to-point interconnect. Such a static configuration provides limited routing options and is not very flexible.

FIG. 1A is a functional block diagram illustrating a prior art multiplexer 102. Multiplexer 102 includes an output 106 and inputs 104 a and 104 b. FIG. 1B is a circuit diagram illustrating multiplexer 102. As is shown in FIG. 1B, multiplexer 102 basically comprises a switch 108 having two states. The first state is to couple input 104 a to output 106. The second state is to couple input 104 b to output 106. Multiplexer 102 essentially operates as an N to 1 multiplexer, where N is the number of inputs (e.g. 2 as in multiplexer 102) and “1” is the number of outputs 106.

BRIEF DESCRIPTION OF THE DRAWINGS

Non-limiting and non-exhaustive embodiments of the invention are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

FIG. 1A is a functional block diagram illustrating a prior art multiplexer.

FIG. 1B is a circuit diagram illustrating a prior art multiplexer.

FIG. 2 is a functional block diagram illustrating a configurable bus, in accordance with an embodiment of the invention.

FIG. 3 is a functional diagram illustrating an integrated circuit with a configurable bus, in accordance with an embodiment of the invention.

FIG. 4A is a flow chart illustrating a process for configuring a configurable bus, in accordance with an embodiment of the invention.

FIG. 4B is a flow chart illustrating a process for multiplexing input/output (I/O) ports coupled to a configurable bus, in accordance with an embodiment of the invention.

FIG. 4C is a flow chart illustrating a process for measuring the capacitance of a capacitor coupled to an I/O port of a configurable bus, in accordance with an embodiment of the invention.

FIG. 5 is a circuit diagram illustrating a switch of a configurable bus, in accordance with an embodiment of the invention.

FIG. 6 illustrates a demonstrative integrated circuit for implementing an embodiment of the invention.

DETAILED DESCRIPTION

Embodiments of a configurable bus are described herein. In the following description numerous specific details are set forth to provide a thorough understanding of the embodiments. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

FIG. 2 is a functional block diagram illustrating a configurable bus 200, in accordance with an embodiment of the invention. The illustrated embodiment of configurable bus 200 includes input/output (I/O) ports 202, bus segments 204, access switches 206, access lines 208, a cross-couple unit 210, a microprocessor 212, and a switch register 214.

In the illustrated embodiment, I/O ports 202 are coupled to bus segments 204 via access switches 206. In one embodiment, some or all of I/O ports 202 are coupled directly to bus segments 204 without access switches 206. I/O ports 202 represent a point of access onto configurable bus 200 and may include a printed circuit board pad, a metal electrode, a wire, a pin, a lead, an integrated circuit leg, a trace, a package ball, or any other conductive path for connecting to configurable bus 200.

In the illustrated embodiment, access switch 206 is coupled between I/O port 202 and bus segment 204 to couple and decouple I/O port 202 to and from bus segment 204. In one embodiment, access switches 206 are configured to allow selective enablement of access switches 206. That is, an individual access switch 206 can be closed while the remaining access switches 206 are open. In one embodiment, one or more access switches 206 can be closed while the remaining access switches 206 are open. In one embodiment, any combination of access switches 206 can be closed and opened at the same time.

The illustrated embodiment of configurable bus 200 includes n number of I/O ports 202 coupled tom number of bus segments 204. In one embodiment, each bus segment 204 is coupled to at least one plurality of I/O ports 202. In one embodiment, bus segment 204 is coupled to one or more I/O ports 202.

Bus segments 204 are coupled to cross-couple unit 210. Cross-couple unit 210 is configurable to selectively couple any of bus segments 204 together. In one embodiment, cross-couple unit 210 can be configured to couple one bus segment 204 to another bus segment 204. In one embodiment, cross-couple unit 210 can be configured to couple two or more bus segments 204 together while decoupling one or more other bus segments 204. In one embodiment, cross-couple unit 210 can be configured to couple two or more bus segments 204 together while separately coupling two or more other bus segments 204 together.

In the illustrated embodiment cross-couple unit 210 and access switches 206 are controlled by switch register 214. In one embodiment, switch register 214 includes a multi-bit control register coupled to microprocessor 212. In one embodiment, switch register 214 includes a static or dynamic shift register having logic elements such as, gates, flip-flops, and the like. By selectively setting switch register 214, microprocessor 212 can independently control each of access switches 206 and the configuration of cross-couple unit 210.

Access lines 208 are also coupled to cross-couple unit 210. In the illustrated embodiment, configurable bus 200 includes an i number of access lines 208. In one embodiment, configurable bus 200 includes one access line 208 for every bus segment 204. In one embodiment, configurable bus 200 includes more or less access lines 208 than there are bus segments 204.

In one embodiment, microprocessor 212 can be programmed to control switch register 214 to multiplex all or a portion of I/O ports 202 onto one or more of access lines 208. For example, microprocessor 212 can set switch register 214 to multiplex n I/O ports 202 to i access lines 208. Microprocessor 212 can also set switch register 214 to reconfigure cross-couple unit 210 to multiplex n I/O ports 202 to any number of access lines 208. By way of another example, some of I/O ports 202 can be multiplexed to one or more access lines 208, while other I/O ports 202 can be simultaneously multiplexed to different access lines 208.

In one embodiment, configurable bus 200 can act to selectively interconnect various devices that are coupled to configurable bus 200. In one embodiment, two or more access switches 206, coupled to the same bus segment 204, can be closed to connect two or more I/O ports 202 together. In one embodiment, I/O ports 202 from different bus segments 204 are coupled together by selectively closing access switches 206 and configuring cross-couple unit 210 to couple two or more bus segments 204 together.

In one embodiment, bus segments 204, access switches 206, cross-couple unit 210 and access lines 208 are capable of conducting analog signals (e.g., continuously variable signals as opposed to discretely variable signals).

FIG. 3 is a circuit diagram illustrating an integrated circuit 300 with a configurable bus, in accordance with an embodiment of the invention. In one embodiment, integrated circuit (IC) 300 represents one possible implementation of configurable bus 200. The illustrated embodiment of IC 300 includes I/O ports 202, access switches 206, microprocessor 212, switch register 214, a die 302, bus segments 304 a-d, access lines 308 a-d, cross-couple unit 310, capacitance measurement circuits 312 a and 312 b, an analog block array 318, other hardware 320 and a system bus 322. The illustrated embodiments of capacitance measurement circuits 312 a and 312 b include capacitance sense circuits 314 a and 314 b, respectively and digital to analog converters (DAC) 316 a and 316 b, respectively. The illustrated embodiment of cross-couple unit 310 includes cross-point switches (CPSW) 306 a-d.

In one embodiment, IC 300 is fabricated on a wafer of electronic-grade silicon (EGS) through known processes, such as lithography. IC 300 is then removed from the wafer to form die 302. Die 302 may be incorporated into any known IC package type including, but not limited to, dual in-line packages (DIP), pin grid arrays (PGA), leadless chip carriers (LLC), surface mount packages (e.g., small-outline integrated circuit), plastic leaded/leadless chip carrier packages (PLCC), plastic quad flat packs (PQFP), ball grid arrays (BGA), and the like. In addition, die 302 may be combined with other dies to form a system in package (SIP) or a multi-chip module (MCM).

IC 300 includes a plurality of I/O ports 202 coupled to at least one of bus segments 304 a-d via access switches 206. Although FIG. 3 illustrates a plurality of I/O ports 202 coupled to each of bus segments 304 a-d, it is recognized that one or more I/O ports 202 may be coupled to each of bus segments 304 a-d. For example, bus segment[1] 304 a can be coupled to one I/O port 202, while bus segment 304 b can be coupled to two or more I/O ports 202. Also, although FIG. 3 illustrates 17 total I/O ports 202, it is recognized that any total number of I/O ports 202 may be coupled to bus segments 304 a-d. In addition, IC 300, in one embodiment, can include I/O ports 202 that are not coupled to any of bus segments 304 a-d.

In the illustrated embodiment, IC 300 includes analog block array 318 coupled to bus segments 304 a-d via access (ACS) lines 308 a-d. Analog block array 318 may include a plurality of user modules (UMs) that are configurable to create a variety of analog signal flows. For example, analog block array can be configured to implement a variety of analog circuits such as, analog-to-digital converters, analog filters, buffers, instrumentation amplifiers, comparators, current output drivers, reference voltages, modulators, correlators, peak detectors, etc. Although FIG. 3 illustrates four access lines 308 a-dand four bus segments 304 a-d, IC 300 can be fabricated with any number of access lines and bus segments.

In the illustrated embodiment, cross-couple unit 310 is coupled to bus segments 304 a-d and includes four cross-point switches (CPSW) 306 a-d. CPSW1 306 a is coupled between bus segment[1] 304 a and bus segment[2] 304 b. CPSW2 306 b coupled between bus segment[1] 304 a and bus segment[3] 304 c. CPSW3 306 c is coupled between bus segment[2] 304 b and bus segment[4] 304 d. CPSW4 304 d is coupled between bus segment[3] 304 c and bus segment[4] 304 d. Although FIG. 3 illustrates four cross-point switches 306 a-d, cross-couple unit 310 may include more or less cross-point switches dependent, in part, on the number of bus segments.

Each of cross-point switches 306 a-d and access switches 206 are coupled to switch register 214 to allow independent control of each switch. That is, each access switch 206 can be closed or opened independently of the other access switches 206 and each cross-point switch 306 a-dcan be closed or opened independently of the other cross-point switches 306 a-d.

In the illustrated embodiment, switch register 214 is controlled by microprocessor 212 via system bus 322. In one embodiment, microprocessor 212 communicates with switch register 214 via memory-mapped I/O (MMIO). In one embodiment microprocessor 212 communicates with switch register 214 via port-mapped I/O (PMIO).

In one embodiment, microprocessor 212 can be programmed to control switch register 214 to multiplex all or a portion of I/O ports 202 onto one or more of access lines 308 a-d. For example, microprocessor 212 can set switch register 214 to open all of cross-point switches 306 a-d and selectively control access switches 206 to multiplex the I/O ports on bus segment[1] to access line[1]; those on bus segment[2] to access line[2], etc. Microprocessor 212 can also set switch register 214 to reconfigure cross-couple unit 210 to multiplex n I/O ports 202 to any number access lines 308 a-d. By way of another example, microprocessor 212 can set switch register 214 to close CPSW2 306 b and CPSW3 306 c while leaving CPSW1 306 a and CPSW4 306 d open. Such a configuration couples bus segment[1] to bus segment[3] and bus segment[2] to bus segment[4]. This configuration also effectively couples access line 308 a to access line 308 c and access line 308 b to access line 308 d, thereby creating two effective access lines coupled to analog block array 318. Thus, access switches can be selectively controlled to multiplex n I/O ports to the two effective access lines. By configuring cross-point switches 306 a-d and selectively enabling access switches 206, the illustrated embodiment of IC 300 can be controlled to multiplex n I/O ports to one, two, three, or four access lines.

In one embodiment, IC 300 can be configured to selectively interconnect various devices that are coupled to any of I/O ports 202. In one embodiment, two or more access switches 206 coupled to the same bus segment 304 a-d, can be closed to connect two or more I/O ports 202 together. By way of example, I/O port[1] and I/O port[n] are both coupled to bus segment[1] and can be coupled together by closing their respective access switches. In one embodiment, I/O ports 202 from different bus segments 304 a-d can be coupled together by selectively closing access switches 206 and configuring cross-couple unit 310 to couple two or more bus segments 304 a-d together. For example, I/O port[1] (coupled to bus segment [1]) and I/O port[2] (coupled to bus segment [2]) can be coupled together by closing CPSW1 306 a and by closing their respective access switches 206.

The illustrated embodiment of IC 300 includes capacitance measurement circuit 312 a coupled to bus segment[1] 304 a and capacitance measurement circuit 312 b coupled to bus segment[3] 304 c. In one embodiment capacitance measurement circuits 312 a and 312 b are used to sense changes in capacitance on device under test (“DUT”) capacitors 320 a and 320 b, each having a changing capacitance. In one embodiment, DACs 316 a and 316 b are set by microprocessor 212 via system bus 322 to output a particular current onto one or more bus segments 304 a-d. Although FIG. 3 only illustrates two capacitance measurement circuits 312 a and 312 b, IC 300 can include one or more capacitance measurement circuits coupled to one or more bus segments 304 a-d.

In one embodiment bus segments 304 a-d are routed on a periphery of die 302. Routing bus segments 304 a-d on the periphery of die 302 can reduce differences in the resultant noise factors on each I/O port 202 because each signal path has a similar, if not identical path through die 302. In one embodiment, bus segments 304 a-d include pairs of bus segments routed substantially in parallel on the periphery of die 302. For example, the illustrated embodiment of IC 300 includes bus segment[1] routed substantially in parallel with bus segment[2] on a left-side periphery of die 302. Also, bus segment[3] is routed substantially in parallel with bus segment[4] on a right-side periphery of die 302. Routing bus segments 304 a-d substantially in parallel can increase the signal to noise ratio of the bus segment pair if configured to perform analog functions such as, differential signaling.

FIG. 4A is a flow chart illustrating a process 400 for configuring a configurable bus, in accordance with an embodiment of the invention. In one embodiment, process 400 is executed by configurable bus 200. In one embodiment, process 400 is executed by IC 300. Process 400 is described with reference to FIGS. 3, 4A, 4B, and 4C. The order in which some or all of the process blocks appear in process 400 should not be deemed limiting. Rather, one of ordinary skill in the art having the benefit of the present disclosure will understand that some of the process blocks may be executed in a variety of orders not illustrated.

In a process block 402, switch register 214 is set. In one embodiment, switch register 214 is set by microprocessor 212 via system bus 322. In a process block 404, cross-couple unit 310 is configured by switch register 214 to selectively couple any of bus segments 304 a-d together. In one embodiment, cross-couple unit 310 is configured by selectively enabling cross-point switches 306 a-d. In one embodiment, cross-couple unit can be configured to decouple two or more of bus segments 304 a-d while coupling two or more other of bus segments 304 a-d. For example, CPSW1 306 a can be closed to couple bus segment[1] to bus segment[2] while CPSW2 306 b and CPSW4 306 d are opened to decouple bus segment[3] from any of the other bus segments 304 a-d.

In a process block 406, switch register 214 selectively enables at least one of the access switches 206 to couple I/O port 202 to at least one of bus segments 304 a-d. For example, I/O port[1] and DUT capacitor 320 a can be coupled to bus segment[1] by closing its respective access switch 206.

Following process block 406, IC 300 can then be configured to execute any of process blocks 410, 412, or 414. In one embodiment, IC 300 executes one of process blocks 410, 412, and 414. In one embodiment, IC 300 simultaneously executes two or more of process blocks 410, 412, and 414. In one embodiment, IC 300 sequentially performs any combination of process blocks 410, 412, and 414.

In process block 410, switch register 214 is configured to interconnect two or more of I/O ports 202. In one embodiment, two or more access switches 206, coupled to the same bus segment 304 a-d, are closed to connect two or more I/O ports 202 together. By way of example, two access switches 206, coupled to I/O port[1] and I/O port[n], are closed to couple these two I/O ports together on bus segment[1]. In one embodiment, I/O ports 202 from different bus segments 304 a-d are coupled together by selectively closing access switches 206 and configuring cross-couple unit 310 to couple two or more bus segments 304 a-d together. By way of another example, I/O port[1] (coupled to bus segment [1]) and I/O port[2] (coupled to bus segment [2]) are coupled together by closing CPSW1 306 a and by closing their respective access switches 206.

In process block 412, I/O ports 202 are multiplexed to analog block array 318 via access lines 308 a-d. FIG. 4B is a flow chart illustrating process block 412, in detail, in accordance with an embodiment of the invention.

In a process block 420, switch register 214 is set by microprocessor 212. In response, switch register 214 configures cross-couple unit 310 by selectively enabling cross-point switches 306 a-din a process block 422.

In a process block 424, switch register 214 selectively enables access switches 206 and in block 426 n I/O ports are multiplexed onto any number of access lines 308 a-d. In one embodiment, microprocessor 212 is programmed to control switch register 214 to multiplex all or a portion of I/O ports 202 onto one or more of access lines 308 a-d. For example, microprocessor 212 can set switch register 214 to open all of cross-point switches 306 a-d and selectively control access switches 206 to multiplex the I/O ports on bus segment[1] to access line[1]; those on bus segment[2] to access line[2], etc.

In a process block 428, switch register 214 is set to reconfigure cross-couple unit 310 to multiplex n I/O ports 202 to any number of access lines 308 a-d. By way of example microprocessor 212 sets switch register 214 to close CPSW2 306 b and CPSW3 306 c while leaving CPSW1 306 a and CPSW4 306 d open. Such a configuration couples bus segment[1] to bus segment[3] and bus segment[2] to bus segment[4]. This configuration also effectively couples access line 308 a to access line 308 c and access line 308 b to access line 308 d, thereby creating two effective access lines coupled to analog block array 318. Thus, access switches can be selectively controlled in a process block 430 to multiplex n I/O ports to the two effective access lines. By configuring cross-point switches 306 a-d and selectively enabling access switches 206, the illustrated embodiment of IC 300 can be controlled to multiplex n I/O ports to one, two, three, or four access lines. In one embodiment, switch register 214 is configured to multiplex n I/O ports on one access line 308 a-d and then multiplex the same n I/O ports on a second access line 308 a-d. For example, all or a portion of I/O ports 202 can be multiplexed to access line 308 a. Switch register 214 then reconfigures cross-couple unit 310 and selectively controls access switches 206 to multiplex all or a portion of I/O ports to access line 308 c.

Referring now back to FIG. 4A, a process block 414 measures the capacitance of DUT capacitors 320 a and 320 b. FIG. 4C is a flow chart illustrating process block 414, in detail, in accordance with an embodiment of the invention.

In a process block 440, switch register 214 is set by microprocessor 212. In response, switch register 214 configures cross-couple unit 310 by selectively enabling cross-point switches 306 a-d in a process block 442.

In a process block 444, switch register 214 selectively enables access switches 206 and in a process block 446, DUT capacitor 320 a is coupled to bus segment[1] and DUT capacitor 320 b is coupled to bus segment[3]. In a process block 448, switch register 214 configures cross-couple unit 310 to couple capacitance measurement circuits 312 a and 312 b to the appropriate bus segments 304 a-d. For example, DUT capacitor 320 a is shown in FIG. 3 as coupled to bus segment[1] and DUT capacitor 320 b is shown as coupled to bus segment[3]. In this example, CPSW2 306 b is opened to allow for independent measurement of the two DUT capacitors. However, in one embodiment, DUT capacitor 320 a can be coupled another of bus segments 304 a-d, such as bus segment[2]. If so, CPSW1 is closed to couple capacitance measurement circuit 312 a to bus segment[2].

In a process block 450, DACs 316 a and 316 b are set by microprocessor 212 via system bus 322 to inject a current into their respective bus segments 304 a-d. In a process block 452, as current is injected into the bus segments, DUT capacitors 320 a and 320 b are charged. In a process block 454 capacitor 320 a is discharged to capacitance sense circuit 314 a and capacitor 320 b is discharged to capacitance sense circuit 314 b. In one embodiment, capacitance sense circuits 314 a and 314 b sense a change in capacitance and transmit a trigger to microprocessor 212 indicating a change in capacitance. In one embodiment, capacitance sense circuits 314 a and 314 b measure the capacitance on DUT capacitors 320 a and 320 b and generate a signal representative of that capacitance. In one embodiment, the signal is sent either directly or via system bus 322 to microprocessor 212. In one embodiment, capacitance sense circuits 314 a and 314 b are coupled to analog block array 318 via cross-couple unit 310 to condition or manipulate the signal representing the capacitance of DUT capacitors 320 a and 320 b.

FIG. 5 is a circuit diagram illustrating a switch 500 of a configurable bus, in accordance with an embodiment of the invention. In one embodiment, switch 500 represents one possible implementation of access switches 206. In one embodiment, switch 500 represents one possible implementation of cross-point switches 306 a-d. The illustrated embodiment of switch 500 includes a FET 504 a coupled in series with a FET 504 b. The illustrated embodiment of switch 500 also includes a FET 504 c connected to a junction 506 between FETs 504 a and 504 b. Also included is inverter 508 coupled at least to a gate of FET 504 c.

Although FIG. 5 shows FETs 504 a and 504 b as complimentary metal oxide field effect transistors (CMOSFETs), FETs 504 a and 504 b may include any device for selectively coupling NODE1 to NODE2 such as, a metal oxide semiconductor FET (MOSFET), a junction FET (JFET), metal semiconductor FET (MESFET), High Electron Mobility Transistor (HEMT), a heterostructure FET (HFET), a modulation doped FET (MODFET), and the like.

FET 504 c is coupled to shunt communication between NODE1 and NODE2, while FETs 504 a and 504 b are off. In the illustrated embodiment, FET 504 c is coupled between junction 506 and a voltage rail (e.g., ground or voltage source). In one embodiment FET 504 c is coupled between junction 506 and a quiet signal. In this embodiment, the quiet signal includes a voltage which may or may not be a ground or supply, but has a relatively small amount of interfering noise from other sources (e.g., interferors and thermal). In one embodiment, FET 504 c is coupled between junction 506 and a reference voltage. In the illustrated embodiment, Inverter 508 is coupled to enable FET 504 c while disabling FETs 504 a and 504 b. Inverter 508 is also coupled to disable FET 504 c while simultaneously enabling FETs 504 a and 504 b.

In one embodiment, switch 500 is configured to operate as any of access switches 206. In this embodiment, NODE1 is coupled to I/O port 202 and NODE2 is coupled to at least one bus segment 204 or bus segments 304 a-d.

In one embodiment, switch 500 is configured to operate as any of cross-point switches 306 a-d. In this embodiment, NODE1 and NODE2 are each coupled to at least one of bus segments 304 a-d.

FIG. 6 illustrates a demonstrative integrated circuit (“IC”) 600 implemented using an embodiment of configurable bus 200 or IC 300. IC 600 may include a Programmable System on a Chip (PSoC™) microcontroller by Cypress Semiconductor Corporation. The illustrated embodiment of IC 600 includes input/output (“I/O”) ports 602. I/O ports 602 are coupled to Programmable Interconnect and Logic (“PIL”) 604 which acts as an interconnect between I/O ports 602 and a digital block array 606. Digital block array 606 may be configured to implement a variety of digital logic circuits (e.g., DAC, digital filters, digital control systems, etc.) using configurable user modules (“UMs”). Digital block array 606 is further coupled to a system bus 614.

Static Random Access Memory (“SRAM”) 610 and microprocessor 612 are also coupled to system bus 614. Microprocessor 612 is coupled to non-volatile storage (“NVS”) 616 which may be used to store firmware (e.g., control algorithms executable by microprocessor 212 to implement process 400).

An analog block array 618 is coupled to system bus 614. Analog block array 618 also may be configured to implement a variety of analog circuits (e.g., ADC, analog filters, comparators, current sources, etc.) using configurable UMs. Analog block array 618 is also coupled to a configurable bus 622 which is coupled to I/O ports 602 and system bus 614. Configurable bus 622 may include an embodiment of configurable bus 200, bus segments 304 a-d, cross-couple unit 210 or 310, access switches 206, access lines 208 or 308 a-d, switch register 214 or capacitance measurement circuits 312 a and 312 b. As illustrated, configurable bus 622 may also be incorporated into IC 600 for coupling to an externally coupled DUT capacitor 620 via I/O ports 602.

The processes explained above are described in terms of computer software and hardware. The techniques described may constitute machine-executable instructions embodied within a machine (e.g., computer) readable medium, that when executed by a machine will cause the machine to perform the operations described. Additionally, the processes may be embodied within hardware, such as an application specific integrated circuit (“ASIC”) or the like. The order in which some or all of the process blocks appear in each process should not be deemed limiting. Rather, one of ordinary skill in the art having the benefit of the present disclosure will understand that some of the process blocks may be executed in a variety of orders not illustrated.

As described above, configurable bus 200 or IC 300 may be incorporated into IC 600, as well as, various other integrated circuits. Descriptions of configurable bus 200 or IC 300 may be generated and compiled for incorporation into other integrated circuits. For example, behavioral level code describing configurable bus 200, or portions thereof, may be generated using a hardware descriptive language, such as VHDL or Verilog, and stored to a machine-accessible medium. Furthermore, the behavioral level code can be compiled into register transfer level (“RTL”) code, a netlist, or even a circuit layout and stored to a machine-accessible medium. The behavioral level code, the RTL code, the netlist, and the circuit layout all represent various levels of abstraction to describe configurable bus 200 or IC 300.

The above description of illustrated embodiments of the invention, including what is described in the Abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of, and examples for, the invention are described herein for illustrative purposes, various modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize.

These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed to limit the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is to be determined entirely by the following claims, which are to be construed in accordance with established doctrines of claim interpretation. 

What is claimed is:
 1. A device, comprising: an analog block array; a first analog bus segment coupled to the analog block array; a second analog bus segment coupled to the analog block array; a third analog bus segment coupled to the analog block array; a first I/O pin selectively couplable to the first analog bus segment; a second I/O pin selectively couplable to the second analog bus segment; a third I/O pin selectively couplable to the third analog bus segment; a first switch configured to selectively propagate a first analog signal on the first analog bus segment to the second analog bus segment; and a second switch configured to selectively propagate a second analog signal on the first analog bus segment to the third analog bus segment; wherein in a first mode of operation, the first and second switches are open, in a second mode of operation, the first switch is closed, and in a third mode of operation, the second switch is closed.
 2. The device of claim 1, further comprising a fourth analog bus segment, wherein: in the second mode of operation, the fourth analog bus segment is connected to the third analog bus segment and is disconnected from the first analog bus segment and the second analog bus segment, and in the third mode of operation, the fourth analog bus segment is connected to the second analog bus segment and is disconnected from the first analog bus segment and the third analog bus segment.
 3. The device of claim 2, wherein the first and second analog bus segments are each located nearer to a first edge of an integrated circuit chip on which the device resides than either of the third and fourth analog bus segments, and wherein the third and fourth analog bus segments are each located nearer to a second edge of the integrated circuit chip opposite the first edge than either of the first and second analog bus segments.
 4. The device of claim 1, wherein each of the first I/O pin, the second I/O pin, and the third I/O pin is selectively connectable to no more than one of the first analog bus segment, the second analog bus segment, and the third analog bus segment.
 5. The device of claim 1, wherein the analog block array comprises reconfigurable analog circuitry.
 6. The device of claim 1, further comprising a set of capacitance sensing circuits each connected to one of the first analog bus segment, the second analog bus segment, and the third analog bus segment, and each configured to measure an external capacitance connected to one of the first I/O pin, the second I/O pin, and the third I/O pin.
 7. The device of claim 6, wherein each capacitance sensing circuit in the set of capacitance sensing circuits is configured to transmit a trigger signal to a microprocessor in response to a change in the external capacitance.
 8. The device of claim 1, further comprising a set of digital-to-analog converters (DACs), wherein each DAC of the set of DACs is configured to, based on input from a microprocessor, inject a current into one of the first analog bus segment, the second analog bus segment, and the third analog bus segment.
 9. The device of claim 1, further comprising a switch register coupled with a microprocessor, wherein the switch register is configured to control the first switch and the second switch based on data written to the switch register by the microprocessor.
 10. The device of claim 1, further comprising a set of digital-to-analog converters (DACs), wherein each DAC of the set of DACs is configured to, based on input from a microprocessor, inject a current into one of the first analog bus segment, the second analog bus segment, and the third analog bus segment.
 11. The device of claim 1, further comprising a system bus configured to couple the analog block array with a microprocessor and with a switch register for controlling the first and second switches, wherein the analog block array and the switch register reside on an integrated circuit with the microprocessor.
 12. A system, comprising: a microprocessor; an analog block array; a first analog bus segment coupled to the analog block array; a second analog bus segment coupled to the analog block array; a third analog bus segment coupled to the analog block array; a first I/O pin selectively couplable to the first analog bus segment; a second I/O pin selectively couplable to the second analog bus segment; a third I/O pin selectively couplable to the third analog bus segment; a first switch configured to selectively propagate a first analog signal on the first analog bus segment to the second analog bus segment; and a second switch configured to selectively propagate a second analog signal on the first analog bus segment to the third analog bus segment; wherein in a first mode of operation, the first and second switches are open, in a second mode of operation, the first switch is closed, and in a third mode of operation, the second switch is closed.
 13. The system of claim 12, further comprising a switch register coupled with the microprocessor, wherein the switch register is configured to control the first switch and the second switch based on data written to the switch register by the microprocessor.
 14. The system of claim 12, further comprising a set of capacitance sensing circuits each connected to one of the first analog bus segment, the second analog bus segment, and the third analog bus segment, and each configured to transmit a trigger signal to the microprocessor in response to a change in an external capacitance.
 15. The system of claim 12, further comprising a set of capacitance sensing circuits each connected to one of the first analog bus segment, the second analog bus segment, and the third analog bus segment, and each configured to measure an external capacitance connected to one of the first I/O pin, the second I/O pin, and the third I/O pin and indicate to the microprocessor a change in the external capacitance.
 16. The system of claim 12, further comprising a set of digital-to-analog converters (DACs), wherein each DAC of the set of DACs is configured to, based on input from the microprocessor, inject a current into one of the first analog bus segment, the second analog bus segment, and the third analog bus segment.
 17. The system of claim 12, wherein the analog block array comprises reconfigurable analog circuitry.
 18. The system of claim 12, further comprising a system bus configured to couple the microcontroller with the analog block array and with a switch register for controlling the first switch and the second switch, wherein the analog block array and the switch register reside on an integrated circuit with the microcontroller.
 19. The system of claim 12, further comprising a fourth analog bus segment, wherein: in the second mode of operation, the fourth analog bus segment is connected to the third analog bus segment and is disconnected from the first analog bus segment and the second analog bus segment, and in the third mode of operation, the fourth analog bus segment is connected to the second analog bus segment and is disconnected from the first analog bus segment and the third analog bus segment.
 20. The system of claim 19, wherein the first and second analog bus segments are each routed along a first portion of a perimeter of an integrated circuit chip on which the microprocessor and the analog block array reside, and wherein the third and fourth analog bus segments are each routed along a second portion of the perimeter of the integrated circuit chip. 